1. Field of the Invention
The present invention relates to a method of fabricating memory cell with transistor, and more particularly to a dynamic random access memory (DRAM) cell having a vertical transistor.
2. Description of the Prior Art
A DRAM cell comprises a metal-oxide-semiconductor field effect transistor (MOSFET) and a capacitor that are built in a semiconductor silicon substrate. There is an electrical contact between the drain of a MOSFET and the bottom storage electrodes of the adjacent capacitor, forming a memory cell of the DRAM device. A large number of memory cells make up the cell arrays which combine with the peripheral circuit to produce DRAMs.
In recent years, the sizes of the MOSFETs have continuously shrunk so that the packing densities of these DRAM devices have increased considerably. For example, new techniques for manufacturing extremely small transistor elements have been developed for 1 Giga bit DRAMs and beyond. One of the methods of increasing integration is to form a three-dimensional transistor structure, instead of the commonly used planar-type transistor.
Referring to FIG. 1A, a semiconductor substrate 100 is provided. A pad oxide layer 102 is formed on the substrate 104 by using an oxidation process. Then, a pad nitride layer 106 and a BPSG layer (not shown) are formed by LPCVD process on the pad oxide 102. The BPSG layer, the pad nitride layer 106, the pad oxide layer 102 and the substrate 100 are defined to form a deep trench 112 by photolithography and etching process. Then, the BPSG layer is removed. At the lower portion of the trench 112, a trench capacitor (not shown) is formed by using conventional process. Then, a thin collar oxide layer 114 is formed on the sidewalls of the upper portion of the deep trench 112 that are above the trench capacitor. A polysilicon layer 116 is formed and fills up the inner space of the deep trench 112.
Referring to FIG. 1B, the polysilicon layer 116 is etched back until the surface of the polysilicon layer 116 in the deep trench 112 is lower than the surface of the substrate 104. Then, the collar oxide layer 114 over the top surface of the polysilicon 116 is over-etched until the top of the collar oxide layer 114 is lower than the top surface of the polysilicon layer 116.
Referring to FIG. 1C, a doped polysilicon layer (not shown) is deposited on the surface of the pad nitride layer 106 and fills the inner space of the deep trench 112. The doped polysilicon layer on the pad nitride layer 106 is removed by a Chemical Mechanical Polishing (CMP) process. The pad nitride layer 106 acts as an etching stop layer while removing the doped polysilicon layer. Then, the doped polysilicon in the deep trench 112 is etched back until the top surface of the doped polysilicon in the deep trench 112 is lower than the surface of the substrate 104 at a predetermined distance. The residual doped polysilicon layer in the deep trench 112 forms the buried strap 122.
Referring to FIG. 1D, an anti-reflection coating (ARC) layer 124 is deposited on the pad nitride layer 106 and fills the inner space of the deep trench 112. A photoresist layer 126 is coated on the anti-reflection coating layer 124, and then afirst opening 128 is defined and formed on the photoresist layer 126 by photolithography.
Referring to FIG. 1E, an opening 130 is formed by anisotropically etching away the anti-reflection coating layer 124, the pad nitride layer 106 , the oxide layer 102, the buried strap 122, the collar oxide layer 114, the first conductive layer 116 and substrate 100. The photoresist layer 126 and the residual ARC layer 124 are then removed.
Referring to FIG. 1F, the opening 130 is filled with an insulating layer (not shown) which may be composed of high density plasma oxide. The pad nitride layer 106, the pad oxide layer 102 and a portion of the insulating layer are planarized by a CMP process, and then the pad nitride layer 106 and the pad oxide layer 102 are removed by an etch-back process. Thus the insulating layer in the opening 130 forms the shallow trench isolation (STI) 136. The impurities contained in the buried strap 122 out-diffuse into the substrate 100 to form the source region 131 because of the high temperature during the mentioned manufacturing processes.
Referring to FIG. 1G, a polysilicon layer (not shown), a tungsten silicide layer (not shown) and a nitride layer (not shown) are sequentially deposited on the surface of the substrate 100 and STI 136. Then, the gates 145 and the second word lines 138 are formed on the surface of the substrate 100 and STI 136 by defining the polysilicon layer, the tungsten silicide layer and the nitride layer by photolithography and anisotropic etching. A drain region 125 is formed by using the gates 145 as the mask and implanting N type dopants into the substrate 100. Thus, the manufacturing of a memory cell with a vertical transistor is completed.
Since the packing density of the DRAM increases and the sizes of the transistors and capacitors continuously scale down, the distance between the source region 131 and the drain region 125 is shortened. Accordingly, the source region 131 tends to overlap with the drain region 125 in the conventional manufacturing process, causing that the gates 145 loss the switching function and the device always turns on. That is, the memory device can not work.
Accordingly, the primary object of the present invention is to provide a method of fabricating a memory cell having a vertical transistor, which can prevent the drain region and the source region from short-circuiting.
According to this invention, a new method of fabricating the semiconductor with a vertical transistor is set forth. The vertical transistor is fabricated in the trench instead of on the surface of the substrate. The gate is located in the trench and extends to the surfaces of the substrate and the shallow trench isolation. The source region and the drain region are then fabricated perpendicularly to each other, and will not overlap with each other. The depth of trench and the location of the gate can be controlled to avoid the overlap of the source region and the drain region.
In order to achieve the above object, this invention provides a method of fabricating a vertical transistor of a memory cell, which is described below. A semiconductor substrate is first provided. A pad layer is formed on the substrate. Then, a deep trench is formed in the substrate. A trench capacitor is formed at the lower portion of the deep trench. A collar oxide layer is formed on the sidewalls of the upper portion of the deep trench that is above trench capacitor. A first conductive layer is formed above said trench capacitor and is etched to a first predetermined depth in said deep trench. A portion of the collar oxide layer above the first conductive layer is removed to form a first opening. A second conductive layer is formed to fill the first opening. An etch-back process is performed to remove a portion of the second conductive layer to a second predetermined depth and have a second opening formed thereon. The residual second conductive layer forms a buried strap. A first insulating layer is formed on the pad layer and extends into the deep trench to cover the sidewalls and bottom of the second opening. Then, a second masking layer is formed on the first insulating layer and fills the inner space of the second opening. A planarization process is performed to remove the portion of the second masking layer and the first insulating layer. The pad layer, the substrate, the second masking layer, the first insulating layer, the collar oxide layer and the first conductive layer are patterned to a third predetermined depth to form a third opening. A second insulating layer is formed to fill the inner space of the third opening. An etching process is performed to remove a portion of the second insulating layer and thus forms a Shallow Trench Isolation. Next, an etch-back process is performed to remove a portion of the second masking layer to a fourth predetermined depth and have a fourth opening formed thereon. Then, the pad layer is removed to expose the surface of the substrate. A third insulating layer is formed on the exposed surface of the substrate and the surface of the second masking layer in the fourth opening. A well is formed at the upper portion of the substrate. The third insulating layer and the first insulating layer covering the substrate in the fourth opening are removed simultaneously while the first insulating layer and the second masking layer are remained on the buried strap. Then, the second masking layer on the bottom of the fourth opening is removed. A fourth insulating layer is formed on the surface of the substrate and on the sidewalls of the fourth opening. The portion of the fourth insulating layer on the top surface of the substrate is removed to form the gate oxide. Sequentially, a third conductive layer and a fourth conductive layer are formed to fill the fourth opening and cover the surface of both the substrate and the shallow trench isolation. Then, the third conductive layer and the fourth conductive layer are defined to form the gate. Finally, the source/drain regions and the gate spacers are formed to complete the fabrication of the vertical transistor of a memory cell.